The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design lpm_rom2.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design lpm_rom2.v has one read port. The read port has 64 words of 16 bits each. The core uses a different clock enable than the input registers. The output of the read port is registered by clock.
The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.
The above waveform shows the behavior of the design under read conditions with clears on input and/or output registers. The read happens at the rising edge of the enabled clock cycle. The read cycle is assumed to be from the rising edge of the clock cycle till the next rising clock edge. The clear on the output register is asynchronous.